Vertical III-V Nanowire Transistors for Low-Power Electronics

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V

Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1

We present vertical InAs/InGaAsSb/GaSb nanowire tunnel FETs (TFETs) on Si demonstrating subthreshold swing (S) of 32 mV/dec with ION = 4 µA/µm for IOFF = 1 nA/µm at VDS = 0.3V. The demonstrated drive currents is the highest reported for a TFET with S below 40 mV/dec resulting in a transconductance efficiency as high as 100 V-1. These results have been achieved by optimizing the source segment growth scheme and the device processing. The devices are compliant with low-power logic applications capable of operation at IOFF = 100 pA/µm

Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S &lt; 100 mV/dec

III-V co-integration is less mature compared to Si/Ge CMOS due to their inferior pMOS device performance. This letter adopts a novel quaternary InGaAsSb channel material in a core-shell vertical nanowire structure to overcome the limitations. A gate-last process achieves self-alignment of the drain and gate contacts. The improved electrostatics with short gate length ${L}_{\text {g}}$ = 60 nm results in a good balance between the on-state and the off-state performances. The presented devices demonstrate the lowest inverse subthreshold slope ( ${S}$ ) for a III-V PMOS with ${S}_{\text {sat}}$ = 75 mV/dec with significant ${I}_{\text {on}}/{I}_{\text {off}}$ ratio of $10^{{4}}$ and ${I}_{\text {min}} <$ 1 nA/ $\mu \text{m}$. The substantial improvement in the device performance compared to earlier reports provides an opportunity for III-V complementary field-effect transistor integration

Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope

Tunnel Field Effect Transistor (TFET), based on band-to-band tunneling, overcomes the thermal limit (subthreshold slope (S) > 60 mV/decade) of the MOSFETs by filtering the high-energy Fermi tail, thereby allowing a substantial reduction of supply voltage and power consumption. Despite the steep slope behavior, TFETs can suffer from ambipolarity wherein carriers tunnel into the channel at both high positive and negative gate voltages. In this work, we demonstrate the fabrication of InAs/InGaAsSb/GaSb vertical nanowire TFET devices and present experimental data showcasing suppressed ambipolarity and a minimum S = 39 mV/decade at Vds=0.05V. The nanowires were grown using MOVPE where the 100nm long InAs drain was n-doped with TESn followed by a 100nm undoped InAs channel and a 100nm/300nm DEZn doped InGaAsSb/GaSb source. After growth, the InAs was selectively digitally etched using citric acid to reduce the channel diameter from 40nm to 25nm. The electrostatics was improved, compared to our previously reported devices, with a gate stack of ALD bilayer of 1nm/3nm Al2O3/HfO2 (EOT~1nm) followed by 30nm sputtered W. To decrease the ambipolar conduction, a gate-drain underlap of approximately 20nm was used which widens the tunnel barrier at the drain junction. Since the gate length is defined by the bottom spacer thickness in vertical transistors, the underlap provides a shorter gate positioned close to the source-channel junction. Thus the new process scheme has improved the slope and reduced the OFF current by one order of magnitude compared to our previous devices [1]. [1] E. Memisevic et al., IEEE Trans.ElectronDevices,vol.64,4746–4751, 2017

Effect of Gate Oxide Defects on Tunnel Transistor RF Performance

Tunnel field-effect transistors (TFETs) are designed for low off-state leakage and low drive voltages. To investigate how capable TFETs are of RF operation, we measured their scattering parameters and performed small-signal modeling. We find that in the low frequency ranges, gate oxide defects have a major influence on the RF performance of these devices, which can be modeled by a frequency-dependent gate-to-drain conductance ggd;w. This model is based on charge trapping in gate oxide defects and was studied before for metal-oxide-semiconductor capacitors

Capacitance Measurements in Vertical III-V Nanowire TFETs

By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well as the charge partitioning of vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain capacitance Cgd is found to largely dominate the on-state of TFETs, whereas the gate-to-source capacitance Cgs is sufficiently small to be completely dominated by parasitic components. This indicates that the tunnel junction on the source side almost completely decouples the channel charge from the small-signal variation in the source, while the absence of a tunnel junction on the drain side allows the channel charge to follow the drain small-signal variation much more directly

Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap

Tunnel Field-Effect Transistors (TFETs) are an emerging alternative to CMOS for ultralow power and neuromorphic applications. The off current (Ioff) and, hence, the subthreshold swing (S) in these devices are limited by ambipolarity, which degrades its capabilities in complementary circuits. Here, we investigate experimentally vertical InAs/InGaAsSb/GaSb nanowire TFETs with gate-drain underlap as a potential solution to avoid ambipolarity and study the temperature dependence of the tunneling current. We compare two different TFET designs, one with an underlap between the gate and drain and the other with an overlap. The introduction of a 25-nm-long underlap region reduced the minimum achievable current Imin from 92 pA/μm to 23 pA/μm by suppressing the ambipolarity and simultaneously improved the minimum S at room temperature from 46 mV/dec to 41 mV/dec at Vds = 0.1 V. We also observe a reduction in the measured on current (Ion) from 0.1 μA/μm in the overlapped device to 0.01 μA/μm in the underlapped device at a drain bias (Vds) = 0.1 V and Ioff = 1 nA/μm. Temperature dependent measurements reveal a potential barrier at the drain junction due to the ungated region at the underlap. We determine a barrier height of 63 meV at Vds = 0.1 V based on thermionic emission combined with a ballistic transport model. Thus, we conclude that gate placement on the drain side is crucial to obtain the low off-currents in TFETs required for ultralow power electronic applications but that the trade-off between Ion and Ioff has to be considered

Flexible thin film pH sensor based on low-temperature atomic layer deposition

Flexible and transparent zinc oxide (ZnO) thin film field-effect transistors (TF-FET) for the use as small volume potentiometric pH sensors are developed. Low temperature atomic layer deposition (ALD) is used for the fabrication of the metal oxides ZnO and aluminum dioxide (Al2O3). Changing the deposition temperature of the ZnO from 150 to 100 °C allowed a significant increase in resistivity by four orders of magnitude. Hence, adjusting the controlled low carrier concentration for the field-effect based sensor is demonstrated. ZnO TF-FET pH sensors fabricated on silicon/silicon dioxide (Si/SiO2) substrates are compared with sensors based on flexible and transparent polyethylene naphthalate (PEN) foil substrates. Comparison of both types of pH sensors showed successful pH sensitivity for pH ranging from 5 to 10 in both cases